With the development of the process technology in recent years, it has become possible to fabricate a high-functionality device, typified by a wireless device, made up of a variety of interconnected circuit blocks, as a one-chip IC (Integrated Circuit).
A filter circuit, which is a circuit block of a radio device, serves to remove signals in unwanted frequency bands. Therefore, the filter circuit is required to have frequency characteristics that are higher in accuracy than the other circuit blocks of the radio device. Usually, the filter circuit incorporates an automatic adjustment circuit for adjusting the difference between designed values and actual frequency characteristics due to fabrication process variations.
One most general means for use as the automatic adjustment circuit of a filter circuit employs a replica made up of a portion of a circuit block of a main filter unit. The replica and the main filter unit are positioned in close proximity with each other on the chip layout for thereby equalizing changes in the frequency characteristic of the replica and the main filter unit due to device variations in the fabrication process. The frequency characteristic of the replica is adjusted, and an adjustment signal applied to the frequency characteristic adjusting terminal of the replica is also applied to the frequency characteristic adjusting terminal of the main filter unit, making it possible to adjust the frequency characteristic of the main filter unit.
FIG. 1 shows, as an example of the frequency characteristic of a general filter, the frequency characteristic of the gain of a second-order BPF (Band-Pass Filter) and the frequency characteristic of the phase thereof.
The frequency characteristics of the gain and the phase are mapped onto each other such that when one of the frequency characteristics is determined, the other frequency characteristic is also determined. If the actual frequency characteristics deviate from design values due to fabrication process variations, then the frequency characteristics of the gain and the phase vary at equal rates, as indicated by the broken lines in FIG. 1. This means that when one of the frequency characteristics of the gain and the phase is adjusted, the other frequency characteristic is also adjusted.
FIG. 2 is a circuit diagram of an automatic adjustment circuit according to the background art.
Replica 9 is made up of a portion of a circuit block of main filter unit 10. Main filter unit 10 and replica 9 have respective frequency characteristic adjusting terminals, and can simultaneously be adjusted. Phase comparator 12 is fed with reference signal 11 and an output signal from replica 9 which is fed with reference signal 11, and outputs an error signal depending on the difference between the phase difference between the input signals and a design value. The error signal is applied to the frequency characteristic adjusting terminal of replica 9 to correct the circuit operation in a direction to make the error signal nil. The circuit operation is finally stabilized when the frequency characteristics of replica 9 and main filter unit 10 are equalized to the design value. The frequency characteristics of replica 9 and main filter unit 10 are thus adjusted to the design value (see Patent documents 1, 2, for example).
In the automatic adjustment circuit according to the background art, as described above, the accuracy with which to adjust the frequency characteristics of the main filter unit depends largely on the phase comparator. In order to increase the accuracy of the phase comparator, the contribution of a parasitic phase delay has to be applied equally to the reference signal and the output signal of the replica.
Consequently, the phase comparator has to be configured fully symmetrically with respect to the reference signal and the output signal of the replica. However, no full symmetry can be achieved by simple configurations of the background art (a double-balanced-mixer phase comparator, a phase comparator employing logic circuits, etc.). If the phase comparator is larger in scale, then the parasitic phase delay increases, making it difficult for the phase comparator to operate at a high speed, and inviting an increase in the chip area and the power consumption.
For the reasons described above, the automatic adjustment circuit according to the background art is problematic in that it is difficult to increase the accuracy with which to adjust the frequency characteristics of the filter circuit.    Patent document 1: JP-A No. 05-299971    Patent document 2: JP-A No. 2003-347901